1. Field of the Invention
The present invention relates to an etching method and a manufacturing method of a thin film transistor.
2. Description of the Related Art
For conventional liquid crystal televisions, amorphous silicon TFTs (thin film transistors) are used in many cases and recognized as structures that can be relatively easily manufactured in terms of manufacturing cost.
However, under current moving image circumstances (e.g., 3D movies or 3D sports broadcast), it is difficult to clearly express moving images with liquid crystal televisions including amorphous silicon TFTs; accordingly, TFTs having high field-effect mobility that can respond at high speed are have been developed. For this reason, a microcrystalline silicon film is under development.
It is known that the field-effect mobility of a thin film transistor in which only a microcrystalline silicon film is employed for a channel formation region is higher than that of an amorphous silicon TFT. On the occasion of employing only a microcrystalline silicon film for a channel formation region for the above-described reason, there is a demand for employing an inverted staggered TFT including a microcrystalline silicon film like the one illustrated in FIG. 7.
A manufacturing method of the inverted staggered TFT illustrated in FIG. 7 is as follows. A gate electrode 102 is formed over a substrate 101, and a gate insulating film 103 is formed over the gate electrode 102. Then, a Si island in which a microcrystalline silicon film 104, an amorphous silicon film 105, and an n+ amorphous silicon film 106 are stacked in this order is selectively formed over the gate insulating film 103, and a conductive film to be processed into a source and drain wirings 110 is formed to cover the Si island.
Next, a resist mask (not shown) is formed over the conductive film, the conductive film is subjected to wet etching using the resist mask as a mask, and the n+ amorphous silicon film 106 is subjected to dry etching. Then, only the amorphous silicon film 105 is subjected to dry etching, so that the microcrystalline silicon film 104 is exposed (e.g., see Patent Document 1). Next, a passivation film 111 is formed over the exposed microcrystalline silicon film 104 and the source and drain wirings 110.
In the case of manufacturing the inverted staggered TFT including the microcrystalline silicon film 104 as a channel formation region in the above-described manner, the n+ amorphous silicon film 106 and the amorphous silicon film 105 need to be etched in a channel etching step. Conventionally, this etching has been carried out using plasma including chlorine or plasma including fluorine with the use of a dry etching apparatus.
However, the difference (and the ratio) between the etching rate of the amorphous silicon film 105 and that of the microcrystalline silicon film 104 is difficult to increase; accordingly, it has been difficult to stop etching at an interface between the microcrystalline silicon film 104 and the amorphous silicon film 105. In other words, there has been a problem in the conventional technique that the microcrystalline silicon film 104 is etched or the amorphous silicon film 105 remains without being completely removed over the substrate plane.
Such a problem is remarkable particularly in the case where a substrate has a large area. This is because in the case of a large-sized substrate, in-plane variation in etching treatment is large and in addition, variations in the film thickness of the amorphous silicon film 105 and the film thickness of the microcrystalline silicon film 104 are also large.
As one means to solve this problem, thickening the microcrystalline silicon film 104 can be considered. However, since the deposition rate of the microcrystalline silicon is particularly lower than that of amorphous silicon, the deposition time is increased in the case of forming the microcrystalline silicon film having a large thickness; as a result, productivity is extremely decreased.